陳信良

陳信良

  • 聯絡電話： +886-2-26215656#55633
  • E-mail：hlchen@mail.tku.edu.tw
  • 個人網站：
  • 學歷： Ph. D., 淡江大學 電機博士
  • 經歷：中國文化大學 電機工程學系 助理教授
    威達高科有限公司 類比設計處 資深類比設計工程師
    工研院 資通所 類比設計工程師
  • 組別：電機資訊組
  • 類別：專任師資
  • 職稱：助理教授
  • 授課科目：電子學、訊號與系統、混合式信號積體電路設計
  • 研究領域：類比數位轉換器、混合式信號積體電路設計、類比積體電路設計
  • 副領域：通訊
期刊論文
  1. Hsin-Liang Chen, Hsiao-Hsing Chou, Hong-Ming Chiu, Hung-Chi Chang and Jen-Shiun Chiang, ” A Second Order Discrete-Time Delta-Sigma Modulator with Successively Approximating Register ADC Assisted Analog Feedback Technique,” IEEE Trans. on VLSI, Submitted.
  2. Hsin-Liang Chen, Hsiao-Hsing Chou, Chun-Kai Fu and Jen-Shiun Chiang,” A 6th Order Current-Mirror-Based Gm-C Bandpass Filter with the Binary Searching Calibration Scheme for Capacitor Sensing Applications,” Analog Integrated Circuits and Signal Processing,
  3. Hsiao-Hsing Chou, Wen-Hao Luo, Hsin-Liang Chen and San-Fu Wang,” A Novel Buck Converter with Dual Loops Control Mechanism,” Electronics, April 2022. http://doi.org/10.3390/electronics11081256.
  4. Hsiao-Hsing Chou and Hsin-Liang Chen,” A Novel Buck Converter with Constant Frequency Controlled Technique,” Energies, Sept. 2021. http://doi.org/10.3390/en14185911.
  5. Hsiao-Hsing Chou, Hsin-Liang Chen, Yang-Hsin Fan and San-Fu Wang, “Adaptive On-Time Control Buck Converter with a Novel Virtual Inductor Current Circuit,” Electronics, Sept. 2021. http://doi.org/10.3390/electronics10172143.
  6. *Hsin Liang Chen, Chi Hsiung Wang and Jen Shiun Chiang, “Reconfigurable Double-Sampled Cascaded Sigma-Delta Modulator with Power Minimizing and System Stabilizing Strategy for Multi-Mode Applications,” Journal of Applied Science and Engineering, Vol. 23, No. 3, pp. 643−654, Dec. 2020. MOST 107-2218-E-034-001-MY2.
  7. *Hsin-Liang Chen, Po-Sheng Chen, and Jen-Shiun Chiang, “Correction to A Low-Offset Low-Noise Sigma-Delta Modulator with Pseudorandom Chopper-Stabilization Technique,” IEEE Trans. on Circuit and System – I: Regular Papers, Vol. 61, No. 3, pp. 957, March 2014.
  8. Yung-Shan Chou, Chun-Chen Lin, Hsin-Liang Chen, and Jen-Shiun Chiang, “Heuristic FIR Filter Design for Cascaded SD Modulators with Finite Amplifier Gain,” IET Circuits, Devices & Systems, Vol. 6, pp. 235-245, July 2012.
  9. *Hsin-Liang Chen, Yi-Tsung Li and Jen-Shiun Chiang, “A Low Power Sigma-Delta Modulator for Dual-Mode Wide-Band Receiver,” Analog Integrated Circuits and Signal Processing, Vol. 71, No. 2, pp. 179-185, May. 2012.
  10. *Hsin-Liang Chen, Po-Sheng Chen, and Jen-Shiun Chiang, “A Low-Offset Low-Noise Sigma-Delta Modulator with Pseudorandom Chopper-Stabilization Technique,” IEEE Trans. on Circuit and System – I: Regular Papers, Vol. 56, No. 12, pp. 2533 – 2543, Dec. 2009.
  11. *Hsin-Liang Chen, Chih-Hao Chen, and Jen-Shiun Chiang, “Inductorless CMOS Receiver Front-End Circuits for 10-Gb/s Optical Communications,” Tamkang Journal of Science and Engineering, Vol. 12, No. 4, pp. 449 – 458, Dec. 2009.
  12. *Jen-Shiun Chiang and Hsin-Liang Chen, “Opamp Gain Insensitive MASH Sigma Delta Modulator for Wide Bandwidth Applications,” Analog Integrated Circuits and Signal Processing, Vol. 47, No. 3, pp. 281 – 291, June 2006.
會議論文
  1. Chuang-Hsuan Chueh, Cheng-Han Lin, Hsin-Liang Chen, Jen-Shiun Chiang, “A Second Order Fully Passive Noise Shaping SAR ADC, ” IET Inter. Conf. on Engineering Technologies and Applications, Nov. 2023.
  2. Yu-Wei Yang, Ting-Yu Syu, Hsin-Liang Chen, Jen-Shiun Chiang, “A 78 dB SNDR 500kHz BW Continuous-Time DSM Hybrid 6-Bit SAR ADC with Sharing DAC, ” IET Inter. Conf. on Engineering Technologies and Applications, Nov. 2023.
  3. Yin-Qin Ye, Sheng-Shiang Lai, Chuang-Hsuan Chueh, Hsin-Liang Chen, and Jen-Shiun Chiang, “A Voltage to Digital Converter for RC Coefficient Calibration in CTDSM with Self-Calibrating Low-Offset Comparator,” The 34rd VLSI Design/CAD Symposium, Aug. 2023.
  4. Yu-Wei Yang, Hung-Chi Chang, Hsin-Liang Chen, and Jen-Shiun Chiang, “A Second Order CT DSM Hybrid 6-Bit SAR ADC with Sharing DAC for Bluetooth Applications,” The 34rd VLSI Design/CAD Symposium, Aug. 2023.
  5. *Hsin-Liang Chen, Yin-Qin Ye, and Jen-Shiun Chiang, “Magnitude to Digital Converter with Latch-Type Comparator and Dynamic Switching Current Scheme,” IET Inter. Conf. on Engineering Technologies and Applications (ICETA), Oct. 2022.
  6. Jo-Chieh Lin, Hsiao-Hsing Chou, and Hsin-Liang Chen, “A Low-Temperature Variation Reference Current Source with Digital Counting Auto-Calibration Scheme,” The 33rd VLSI Design/CAD Symposium, Aug. 2022.
  7. *Hung-Ming Chiu, Yu-Wei Yang, Hsin-Liang Chen, and Jen Shiun Chiang, “High Dynamic Range Audio Multi-bit 2nd Order DT DSM Hybrid SAR ADC with One Sharing DAC,” IEEE Int. Symp. On Intelligent Signal Processing and Communications Systems, Nov. 2021.
  8. *Hsin-Liang Chen, Yu-Chun Chiu, and J. S. Chiang, “Modified Magnitude Detected Converter with Latched-Type Comparator,” The 32nd VLSI Design/CAD Symposium, Aug. 2021.
  9. *Chun-Kai Fu, Hung-Ming Chiu, Hsin-Liang Chen, and Jen Shiun Chiang, “A 6th-Order Current-Mode Gm-C Bandpass Filter with Correlated Gm-C Base LC Oscillator Calibrating Scheme,” The 31th VLSI Design/CAD Symposium, Aug. 2020.
  10. *Hsin-Liang Chen, Ming Han Hsieh, and Jen Shiun Chiang “A Low Distortion 10-Bit Current Steering DAC with Pseudorandom Dynamic Element Matching Technique,” IEEE Int. Symp. On Intelligent Signal Processing and Communications Systems, 2019.
  11. *Hsin-Liang Chen, Jiun Kai Fu, and Jen Shiun Chiang, “A 6th-Order Current-Mode Gm-C Bandpass Filter with Correlated Ring Oscillator Calibrating Scheme,” The 30th VLSI Design/CAD Symposium, Aug. 2019.
  12. Hsin-Liang Chen, and Shu-Chuan Yang, “A 8-Bit 1-GS/s Subranged ADC in 65-nm CMOS Process,” IEEE Int. Symp. On Intelligent Signal Processing and Communications Systems, Nov. 2015.
  13. Hsin-Liang Chen, Su-Chun Cheng, and Bo-Wei Chen, “A 5-GS/s 46-dBc SFDR Track and Hold Amplifier,” IEEE Int. Symp. On Intelligent Signal Processing and Communications Systems, Dec. 2012.
  14. *Chun-Chen Lin, Yung-Shan Chou, Hsin-Liang Chen, and Jen-Shiun Chiang, “Leaky Quantization Noise Reduction for Cascaded Sigma-Delta Modulators using H-infinity Control,” IEEE International Midwest Symposium on Circuits and System, Aug. 2010.
  15. *Hsin-Liang Chen, Jen-Shiun Chiang, “A Low-Power and Multi-Mode Design Approach for Reconfigurable MASH SDM,” IEEE International Conference on IC Design and Technology, pp. 3-6, May 2009.
  16. *Hsin-Liang Chen, Po-Sheng Chen, and Jen-Shiun Chiang, “Digital Compensated Methodology of a 2-1-1 Cascaded Continuous Time Delta-Sigma Modulator,” IEEE International Symposium on Circuits and Systems, May 2009.
  17. *Chun-Yao Lu, Chang-Yu Hsieh, Hsin-Liang Chen, and Jen-Shiun Chiang, “A High-Resolution Time-Interleaved Delta-Sigma Modulator with Low Oversampling,” International Symposium on Integrated Circuits, Dec. 2009.
  18. Hsin-Liang Chen, Yi-Sheng Lee, and Jen-Shiun Chiang, “Low power sigma delta modulator with dynamic biasing for audio applications,” IEEE MWSCAS, Aug. 2007.
  19. *Hsin-Liang Chen, Ming-Chi Tsai, and Jen-Shiun Chiang, “A Low Power Wide Bandwidth Second Order Continuous Time Sigma Delta Modulator with Single Amplifier Scheme”, IASTED International Conference on Circuits, Signals, and Systems, Jul. 2007.
  20. Jen-Shiun Chiang, Yi-Tsung Li, Hsin-Liang Chen, and Ming-Chi Tsai, “A 20-MS/s Sigma Delta Modulator for 802.11a Applications”, IEEE International Symposium on Circuits and Systems, pp. 1888-1891, May 2006.
  21. Fun Ye, Jen-Shiun Chiang, Yi-Tsung Li, Pou-Chu Chou and Hsin-Liang Chen, “A Low Power Sigma Delta Modulator for GSM and W-CDMA Applications,” IEE ADDA, pp. 309-312, July 2005.