Journal Paper
1. Horng-Yuan Shih, Sheng-Kai Lin and Po-Shun Liao, "A 80x Analog-Implemented Time Difference Amplifier for Delay-Line Based Coarse-Fine Time-to-Digital Converters in 0.18-μm CMOS," IEEE Transactions on Very Large Scale Integration Systems, vol. 23, no.8, pp. 1528-1533, Aug. 2015. (SCI)
2. Horng-Yuan Shih, Chun-Fan Chen, Yu-Chuan Chang and Yu-Wei Hu, "An Ultra-Low Power Multi-Rate FSK Demodulator with Digtially Assisted Calibrated Delay-Line Based Phase Shifter for High-Speed Biomedical Zero-IF Receivers," IEEE Transactions on Very Large Scale Integration Systems, vol. 23, no. 1, pp. 98-106, Jan. 2015. (SCI)
3. Horng-Yuan Shih, Chun-Fan Chen and Sheng-Kai Lin, "A 2.24 mW 74 dBΩ-Gain, DC to 600 MHz-BW Differential Baseband Amplifier for 60 GHz Wireless Applications," IEEE Microwave and Wireless Components Letters, vol. 23, no. 3, pp. 152-154, March 2013. (SCI)
4. Horng-Yuan Shih and Yu-Chuan Chang, "68.4 µW 400 MHz Intrabody Communication Receiver Front-end for Biomedical Applications," IET Electronics Letters, vol. 48, issue 3, pp. 143-144, Feb. 2012. (SCI). (Invited as feature article and listed as highlight article)
5. Horng-Yuan Shih and Chih-Wei Wang, "A Highly-Integrated 3-8 GHz Ultra-Wideband RF Transmitter with Digital-Assisted Carrier Leakage Calibration and Automatic Transmit Power Control," IEEE Transactions on Very Large Scale Integration Systems, vol. 20, no. 8, pp. 1357-1367, Aug. 2012. (SCI)
6. Horng-Yuan Shih, Chien-Nan Kuo, et al, "A 250 MHz 14 dB-NF 73 dB-Gain 82 dB-DR Analog Baseband Chain with Digital-Assisted DC-Offset Calibration for Ultra-Wideband," IEEE Journal of Solid-State Circuits, vol. 45, no 2, pp. 338-350, Feb. 2010. (SCI)
Thesis
1. Yu-Chuan Chang, "Design of Ultra-low Power Receiver Front-end in a Sub-micro CMOS Process," 2012. (PDF)
2. Chun-Fan Chen, "An Ulta-Low Power Multi-Rate FSK Demodulator in 0.18 um CMOS Process," 2013. (PDF)
3. Sheng-Kai Lin, "Design of Gain-Adjustable Time Amplifier for Coarse-Fine TDC in 0.18 um CMOS Process," 2013. (PDF)
International Conference Paper
1. Chiou-bang Chen and Horng-Yuan Shih, "A 400 MHz 0.934ps rms Jitter Multiplying Delay Lock Loop in 90-nm CMOS Process," The 17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 (Accepted)
2. Tzu-Chao Yan, Horng-Yuan Shih, Tzu-Yi Yang, and Chien-Nan Kuo, 'A Q-band Direct Divide-by-4 Injection-Locked Frequency Divider with Quadrature Outputs', IEEE European Microwave Conference, 2010. (Accepted)
3. Yu-Lin Tsou, Horng-Yuan Shih, Chien-Nan Kuo and Chia-Hung Chang, ‘Differential LC Ladder LNA with Proposed third-Order Active Notch Filter for UWB Band Group1,’ IEEE International Conference on Ultra-Wideband, pp. 511-515, Sep. 2009.
4. Horng-Yuan Shih, Wei-Hsien Chen, Kai-Chenug Juang, Tzu-Yi Yang and Chien-Nan Kuo, ‘A 1.2V Interference-Sturdiness, DC-Offset Calibrated CMOS Receiver Utilizing a Current-Mode Filter for UWB,’ IEEE Asian Solid-State Circuits Conference, pp. 345-348, Nov. 2008.5. Chao-Shiun Wang, Wei-Chang Li, Chomg-Kuang Wang, Horng-Yuan Shih and Tzu-Yi Yang,’ A 3–10 GHz full-band single VCO agile switching frequency generator for MB-OFDM UWB,’ IEEE Asian Solid-State Circuits Conference, pp. 75-78, Nov. 2007.
6. Horng-Yuan Shih, Tz-Heng Fu, Yen-Horng Chen, et al.,‘Highly-integrated low-power WCDMA SiGe transceiver for mobile terminals,’ IEEE International Microwave Symposium Digest, pp. 93-96, June 2005.
7. Horng-Yuan Shih, Peng-Un Su, Yen-Horng Chen, et al., ‘A highly-integrated inductor-less SiGe W-CDMA transmitter,’ IEEE Radio Frequency Integrated Circuits Symposium Digest of Papers, pp.439 – 442, June 2004.
8. Horng-Yuan Shih,‘A 1.8-GHz Low-Phase-Noise Integrated CMOS LC-VCO with a Low Q Inductor for GSM/DCS Band,’ Asia Pacific Microwave Conference Proceedings, Nov. 2003.
9. S.T. Peng, R.B. Hwang, and H.Y. Shih,‘ Anomalous absorption of resonance-type periodic structures,’ IEEE Antennas and Propagation Society International Symposium, vol. 3, pp. 1792 – 1795, July 2000.
Domestic Conference Paper
1. Horng-Yuan Shih, Huan-Ke Chiu, Tzu-Chan Chueh, et al., '2.5-GHz Hybrid Oscillator with both a Wide Tuning Range and High Frequency Resolution for Digital PLL', 2010 VLSI/CAD Conference. (Accepted)
2. Tzu-Chao Yan, Horng-Yuan Shih, Tzu-Yi Yang, and Chien-Nan Kuo, 'A Q-band Direct Divide-by-4 Injection-Locked Frequency Divider with Quadrature Outputs', 2010 VLSI/CAD Conference. (Accepted)
3. Shih-Hao Tarng, Jia-Hung Peng, Tzu-Chan Chueh, Ming-Ching Kuo and Horng-Yuan Shih, 'An Automatic Frequency Calibration Technique for Fractional-N Frequency Synthesizers', 2010 VLSI/CAD Conference. (Accepted)
4. Yu Lin Tsou, Tim K. Shia, Kai Cheung Juang and Horng Yuan Shih, 'A Low Power Front-End Receiver Design for Sphygmus Sensor Using Pulse-Repetition Period Modulation', 2010 VLSI/CAD Conference. (Accepted)
U.S. Patent
1. Horng-Yuan Shih, Wei-Hsien Chen and Kai-Cheung Juang, 'Current-mode analog baseband apparatus,' U.S. Patent no. 8,441,313.
2. Horng-Yuan Shih, Wei-Hsien Chen and Kai-Cheung Juang, 'Current-mode analog baseband apparatus,' U.S. Patent no. 8,427,230.
3. Horng-Yuan Shih, Wei-Hsien Chen and Kai-Cheung Juang, 'Current-mode Amplifier,' U.S. Patent no. 8,289,080.
4. Chien-Nan Kuo, Horng-Yuan Shih and Yi-Hsin Pang, 'Coherent tunable filter appratus and wireless communication front-end circuit thereof,' U.S. Patent no. 8,073,419.
5. Huan-Ke, Chiu, Horng-Yuan Shih, Chiou-Bang Chen, Tzu-Chan Chueh, 'Pipeline time-to-digital converter,' U.S. Patent no. 7,928,888.
6. Peng-Un Su, Horng-Yuan Shih, Ming-Ching Kuo, 'Device for Voltage-Noise Rejection and Fast Start-Up,' U.S. Patent no. 7,756,226.
7. Kai-Cheung Juang, Wei-Hsien Chen, Horng-Yuan Shih,” DC offset calibration method,” U.S. Patent no. 7,629,906.
8. Peng-Un Su, Chih-Hung Chen, Horng-Yuan Shih,“ Frequency synthesizing device with automatic calibration,” U.S. Patent no. 7,583,773.
9. Kai-Cheung Juang, Horng-Yuan Shih, Peng-Un Su,“ Voltage controlled oscillator with anti supply voltage variation and/or process variation,” U.S. Patent no. 7,449,972.
R.O.C. Patent
1. 施鴻源, 陳威憲, 莊凱翔, "電流式放大器," 中華民國發明專利 No. I413361.
2. 邱煥科, 施鴻源, 陳秋榜, 闕資展,"管線式時間數位轉換器, " 中華民國發明專利 No. I347085.
3. 莊凱翔, 陳威憲, 施鴻源, "直流偏移校正電路及方法," 中華民國發明專利 No. I355829.
4. 蘇秉恩,施鴻源,郭明清,’具電壓雜訊壓抑與快速啟動的裝置,’中華民國發明專利 No. I304289.
5. 蘇秉恩,陳志宏,施鴻源,’自動校正的頻率合成裝置,’中華民國發明專利 No. I241069.
6. 莊凱翔,施鴻源,蘇秉恩,’可抵抗電源變動與/或製程變異之電壓控制振盪器,’中華民國發明專利 No. I264875.
China Patent
1. 邱煥科, 施鴻源, 陳秋榜, 闕資展,"管線式時間數位轉換器, " 中華人民共和國發明專利 No. ZL200910220812.6
2. 莊凱翔, 陳威憲, 施鴻源, "直流偏移校正電路及方法," 中華人民共和國發明專利 No. ZL200810008571.4
3. 郭建男, 施鴻源, 龐一心, '協調性可調式濾波裝置及其無線通信前端電路' 中華人民共和國發明專利 No. ZL 200910003322.0
Award
施鴻源 交大電子所 98年度 博士論文獎-優等獎
News :
2014/07/21
A paper titled 'A 80x Analog-Implemented Time Difference Amplifier for Delay-Line Based Coarse-Fine Time-to-Digital Converters in 0.18-μm CMOS' is accepted by IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
2013/12/29
A paper titled 'An Ultra-Low Power Multi-Rate FSK Demodulator with Digtially Assisted Calibrated Delay-Line Based Phase Shifter for High-Speed Biomedical Zero-IF Receivers' is accepted by IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
2013/05/14
A U.S. patent 'Current-mode analog baseband apparatus'' is certified with patent no.8,441,313.
2013/04/23
A U.S. patent 'Current-mode analog baseband apparatus'' is certified with patent no.8,427,230.
2013/01/27
A paper titled 'A 2.24 mW 74 dBΩ-Gain, DC to 600 MHz-BW Differential Baseband Amplifier for 60 GHz Wireless Applications' is accepted by IEEE Microwave and Wireless Components Letters
2012/11/1
A China patent '協調性可調式濾波裝置及其無線通信前端電路' is certified with patent no. ZL 200910003322.0
2012/10/16
A U.S. patent 'Current-mode Amplifier'' is certified with patent no. 8,289,080.
2012/3/17
A U.S. patent 'Coherent tunable filter appratus and wireless communication front-end circuit thereof' is certified with patent no. 8,073,419.
2012/1/10
A paper titled 'A 68.4 µW 400 MHz Intrabody Communication Receiver Front-end for Biomedical Applications' is accepted by IET Electronics Letters.
2011/7/18
A U.S. patent 'Pipeline time-to-digital converter' is certified with patent no. 7,928,888.
2011/5/17
A paper titled 'A Highly-Integrated 3-8 GHz Ultra-Wideband RF
Transmitter with Digital-Assisted Carrier Leakage Calibration and
Automatic Transmit Power Control' is accepted by IEEE Transactions on Very Large
Scale Integration (VLSI) Systems.
2010/9/26
A paper titled 'A 400 MHz 0.934ps rms Jitter Multiplying Delay Lock
Loop in 90-nm CMOS Process' is accepted by IEEE ICIES 2010.
2010/7/27
Four papers are accepted by 2010 VLSI/CAD Conference.